Electrostatic discharge (ESD) represents an on-going threat to electronic systems, especially integrated circuits (IC) in which a semiconductor device is housed within an IC package. When an IC is exposed to an ESD event, an accumulation of static electricity moves from an external surface to the semiconductor device within the IC package, through one or more of its pins. Common metal-oxide semiconductor field-effect transistors (MOSFETs) and complementary metal-oxide semiconductor (CMOS) devices, which are formed from so called N-type material, P-type material, and insulating material (e.g., thin insulating oxides), are especially vulnerable to ESD. In particular, ESD can cause internal local heating that melts or fractures dielectric silicon oxide that insulates gates from other internal structures, resulting in permanent damage to the IC. Furthermore, ESD can cause drain to source shorts across MOSFET channels (i.e., second breakdown).
After an IC is manufactured and before it is installed on a circuit board, the IC is very susceptible to ESD damage. Conventional procedures for protecting ICs from ESD include making surfaces on shipping containers conductive to prevent or dissipate electrostatic charge buildup, grounding work surfaces, requiring handlers to wear grounded conductive wrist straps and clothing, and maintaining environmental conditions such as humidity and air ionization at levels that reduce the opportunity for electrostatic charge accumulation.
As a further safeguard, the typical IC includes ESD protection circuits that help to insulate more sensitive circuits within the semiconductor device from damage by ESD events. Generally, such ESD protection devices or circuits are located within the semiconductor device itself in close proximity to pads that are used to electrically connect the semiconductor device to the pins of the IC package.
ESD protection diodes and grounded-gate transistors are examples of conventional ESD protection devices. When an electrostatic charge is placed on an input/output (I/O) pin of the IC, i.e., a pin that receives an information bearing I/O signal, the ESD protection diode or grounded-gate transistor shunts the charge from the I/O pin, away from the circuits to be protected, to other areas of the IC such as a power supply pin or a ground pin of the IC.
An ESD protection circuit, which has been used to protect an IC from electrostatic discharge events occurring on an I/O pin, has the ability to disable itself when the IC is powered up. This ESD protection circuit (hereinafter called the "I/O pin protection circuit") has a large N-channel transistor interconnected between the I/O pin and a ground or reference pin, and an inverter (formed by two transistors) having an output that is connected with a gate of the N-channel transistor and an input connected with a power supply pin. If a substantial electrostatic charge is placed on the I/O pin when the IC is not powered up (i.e., when no power supply signal is received by the power supply pin), the large N-channel transistor turns on to provide a pathway between the I/O pin and the reference pin to dissipate the charge. When the IC is powered up (i.e., when a power supply signal is received by the power supply pin), the I/O pin protection circuit is disabled thereby enabling the other circuits of the IC to operate normally.
Another ESD protection circuit (hereinafter called the "power supply pin protection circuits") protects an IC from ESD events occurring on either an I/O power supply pin or a. internal power supply pin. The power supply pin protection circuit includes a first ESD protection device interconnected between the I/O power supply pin and a reference pin to direct electrostatic charge away from drive circuits that are powered via the I/O power supply pin through an I/O conductor Vdd.sub.x. The power supply pin protection circuit further includes a second ESD protection device interconnected between the internal power supply pin and the reference pin to direct electrostatic charge away from internal (non-drive) circuits that are powered by the internal power supply pin through an internal power conductor Vdd.sub.i. The capacitance of the conductor Vdd.sub.i is higher than that of the conductor Vdd.sub.x such that, when the IC is powered up, the power supply signal carried through the conductor Vdd.sub.i is more noise filtered than the power supply signal carried through the conductor Vdd.sub.x. Accordingly, the power supply signal received by the internal circuits is less noisy than the power supply signal received by the drive circuits. When the IC is powered up, the first and second ESD protection devices of the power supply pin protection circuit detect the same power supply signal and are both disabled. When the IC is not powered up (i.e., when neither power supply pin receives a power supply signal), the first and second ESD protection devices operate to detect ESD events by reference to voltages between the power supply pins and the reference pin.